#include <qt8s726.h>

__sfr __at (INDF0_ADDR)         INDF0;
__sfr __at (FSR0_ADDR)          FSR0;
__sfr __at (INDF1_ADDR)         INDF1;
__sfr __at (FSR1_ADDR)          FSR1;
__sfr __at (PCL_ADDR)           PCL;
__sfr __at (STATUS_ADDR)        STATUS;
__sfr __at (OPTION_ADDR)        OPTION;
__sfr __at (OSCM_ADDR)          OSCM;
__sfr __at (WDTC_ADDR)          WDTC;
__sfr __at (IOICR_ADDR)         IOICR;
__sfr __at (INDF2_ADDR)         INDF2;
__sfr __at (HBUF_ADDR)          HBUF;
__sfr __at (INTCR0_ADDR)        INTCR0;
__sfr __at (INTF0_ADDR)         INTF0;
__sfr __at (INTCR1_ADDR)        INTCR1;
__sfr __at (INTF1_ADDR)         INTF1;
__sfr __at (IOA_ADDR)           IOA;
__sfr __at (OEA_ADDR)           OEA;
__sfr __at (PUA_ADDR)           PUA;
__sfr __at (ANSA_ADDR)          ANSA;
__sfr __at (IOB_ADDR)           IOB;
__sfr __at (OEB_ADDR)           OEB;
__sfr __at (PUB_ADDR)           PUB;
__sfr __at (ANSB_ADDR)          ANSB;
__sfr __at (IOLDS_ADDR)         IOLDS;
__sfr __at (IOHDS_ADDR)         IOHDS;
__sfr __at (PDAB_ADDR)          PDAB;
__sfr __at (PWM0CR_ADDR)        PWM0CR;
__sfr __at (PWM0D_ADDR)         PWM0D;
__sfr __at (PWM1CR_ADDR)        PWM1CR;
__sfr __at (PWM1DH_ADDR)        PWM1DH;    
__sfr __at (PWM1DL_ADDR)        PWM1DL;
__sfr __at (PWMDEADT_ADDR)      PWMDEADT;
__sfr __at (T0CR_ADDR)          T0CR;
__sfr __at (TC0CL_ADDR)         TC0CL;
__sfr __at (TC0CH_ADDR)         TC0CH;
__sfr __at (T1CR_ADDR)          T1CR;
__sfr __at (TC1CL_ADDR)         TC1CL;
__sfr __at (TC1CH_ADDR)         TC1CH;
__sfr __at (ADCON2_ADDR)        ADCON2;
__sfr __at (ADCON0_ADDR)        ADCON0;
__sfr __at (ADCON1_ADDR)        ADCON1;
__sfr __at (ADH_ADDR)           ADH;
__sfr __at (ADL_ADDR)           ADL;
__sfr __at (TKCTR0_ADDR)        TKCTR0;

volatile __INDF0bits_t __at(INDF0_ADDR) INDF0bits;
volatile __FSR0bits_t __at(FSR0_ADDR) FSR0bits;
volatile __INDF1bits_t __at(INDF1_ADDR) INDF1bits;
volatile __FSR1bits_t __at(FSR1_ADDR) FSR1bits;
volatile __PCLbits_t __at(PCL_ADDR) PCLbits;
volatile __STATUSbits_t __at(STATUS_ADDR) STATUSbits;
volatile __OPTIONbits_t __at(OPTION_ADDR) OPTIONbits;
volatile __OSCMbits_t __at(OSCM_ADDR) OSCMbits;
volatile __WDTCbits_t __at(WDTC_ADDR) WDTCbits;
volatile __IOICRbits_t __at(IOICR_ADDR) IOICRbits;
volatile __INDF2bits_t __at(INDF2_ADDR) INDF2bits;
volatile __HBUFbits_t __at(HBUF_ADDR) HBUFbits;
volatile __INTCR0bits_t __at(INTCR0_ADDR) INTCR0bits;
volatile __INTF0bits_t __at(INTF0_ADDR) INTF0bits;
volatile __INTCR1bits_t __at(INTCR1_ADDR) INTCR1bits;
volatile __INTF1bits_t __at(INTF1_ADDR) INTF1bits;
volatile __IOAbits_t __at(IOA_ADDR) IOAbits;
volatile __OEAbits_t __at(OEA_ADDR) OEAbits;
volatile __PUAbits_t __at(PUA_ADDR) PUAbits;
volatile __ANSAbits_t __at(ANSA_ADDR) ANSAbits;
volatile __IOBbits_t __at(IOB_ADDR) IOBbits;
volatile __OEBbits_t __at(OEB_ADDR) OEBbits;
volatile __PUBbits_t __at(PUB_ADDR) PUBbits;
volatile __ANSBbits_t __at(PUB_ADDR) ANSBbits;
volatile __IOLDSbits_t __at(IOLDS_ADDR) IOLDSbits;
volatile __IOHDSbits_t __at(IOHDS_ADDR) IOHDSbits;
volatile __PDABbits_t __at(PDAB_ADDR) PDABbits;
volatile __PWM0CRbits_t __at(PWM0CR_ADDR) PWM0CRbits;
volatile __PWM0Dbits_t __at(PWM0D_ADDR) PWM0Dbits;
volatile __PWM1CRbits_t __at(PWM1CR_ADDR) PWM1CRbits;
volatile __PWM1DHbits_t __at(PWM1DH_ADDR) PWM1DHbits;
volatile __PWM1DLbits_t __at(PWM1DL_ADDR) PWM1DLbits;
volatile __PWMDEADTbits_t __at(PWMDEADT_ADDR) PWMDEADTbits;
volatile __T0CRbits_t __at(T0CR_ADDR) T0CRbits;
volatile __TC0CLbits_t __at(TC0CL_ADDR) TC0CLbits;
volatile __TC0CHbits_t __at(TC0CH_ADDR) TC0CHbits;
volatile __T1CRbits_t __at(T1CR_ADDR) T1CRbits;
volatile __TC1CLbits_t __at(TC1CL_ADDR) TC1CLbits;
volatile __TC1CHbits_t __at(TC1CH_ADDR) TC1CHbits;
volatile __ADCON2bits_t __at(ADCON2_ADDR) ADCON2bits;
volatile __ADCON0bits_t __at(ADCON0_ADDR) ADCON0bits;
volatile __ADCON1bits_t __at(ADCON1_ADDR) ADCON1bits;
volatile __TKCTR0bits_t __at(TKCTR0_ADDR) TKCTR0bits;
